// Copyright (c) 2018 ETH Zurich, University of Bologna
// All rights reserved.
//
// This code is under development and not yet released to the public.
// Until it is released, the code is under the copyright of ETH Zurich and
// the University of Bologna, and may contain confidential and/or unpublished
// work. Any reuse/redistribution is strictly forbidden without written
// permission from ETH Zurich.
//
// Bug fixes and contributions will eventually be released under the
// SolderPad open hardware license in the context of the PULP platform
// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
// University of Bologna.
//
// Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
// Date: 15.08.2018
// Description: File list for OpenPiton flow
+incdir+core/include/
+incdir+vendor/pulp-platform/common_cells/include/
+incdir+common/local/util/
+incdir+corev_apu/register_interface/include/

core/include/config_pkg.sv
core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
core/include/riscv_pkg.sv
corev_apu/riscv-dbg/src/dm_pkg.sv
core/cvfpu/src/fpnew_pkg.sv
core/include/ariane_pkg.sv
corev_apu/tb/ariane_soc_pkg.sv
vendor/pulp-platform/axi/src/axi_pkg.sv
corev_apu/tb/ariane_axi_pkg.sv
core/include/wt_cache_pkg.sv
corev_apu/tb/axi_intf.sv
vendor/pulp-platform/common_cells/src/cf_math_pkg.sv
core/include/instr_tracer_pkg.sv
core/cvxif_example/include/cvxif_instr_pkg.sv
core/acc_dispatcher.sv
corev_apu/rv_plic/rtl/rv_plic_reg_pkg.sv
core/cache_subsystem/cva6_hpdcache_wrapper.sv
core/cache_subsystem/cva6_hpdcache_subsystem.sv
core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv
core/cache_subsystem/cva6_hpdcache_subsystem_l15_adapter.sv
core/cache_subsystem/cva6_hpdcache_if_adapter.sv
core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_1rw.sv
core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wbyteenable_1rw.sv
core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wmask_1rw.sv
core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_l15_req_arbiter.sv
core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_l15_resp_demux.sv
core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_to_l15.sv
core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_read_arbiter.sv
core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_resp_demux.sv
core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_write_arbiter.sv
core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_write.sv
core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_read.sv
common/local/util/sram.sv
common/local/util/sram_cache.sv
vendor/pulp-platform/common_cells/src/deprecated/rrarbiter.sv
vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv
vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv
vendor/pulp-platform/common_cells/src/fifo_v3.sv
vendor/pulp-platform/common_cells/src/shift_reg.sv
vendor/pulp-platform/common_cells/src/lfsr_8bit.sv
vendor/pulp-platform/common_cells/src/lfsr.sv
vendor/pulp-platform/common_cells/src/lzc.sv
vendor/pulp-platform/common_cells/src/exp_backoff.sv
vendor/pulp-platform/common_cells/src/rr_arb_tree.sv
vendor/pulp-platform/common_cells/src/rstgen_bypass.sv
vendor/pulp-platform/common_cells/src/cdc_2phase.sv
vendor/pulp-platform/common_cells/src/unread.sv
vendor/pulp-platform/common_cells/src/popcount.sv
corev_apu/axi_mem_if/src/axi2mem.sv
vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv
vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv
common/local/util/tc_sram_wrapper.sv
vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv
vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv
core/cache_subsystem/axi_adapter.sv
core/alu.sv
core/alu_wrapper.sv
core/fpu_wrap.sv
corev_apu/src/ariane.sv
core/include/build_config_pkg.sv
core/cva6_rvfi_probes.sv
core/cva6.sv
core/branch_unit.sv
core/compressed_decoder.sv
core/controller.sv
core/csr_buffer.sv
core/csr_regfile.sv
core/decoder.sv
core/ex_stage.sv
core/frontend/btb.sv
core/frontend/bht.sv
core/frontend/bht2lvl.sv
core/frontend/ras.sv
core/frontend/instr_scan.sv
core/frontend/instr_queue.sv
core/frontend/frontend.sv
core/id_stage.sv
core/instr_realign.sv
core/issue_read_operands.sv
core/issue_stage.sv
core/load_unit.sv
core/load_store_unit.sv
core/lsu_bypass.sv
core/cva6_mmu/cva6_shared_tlb.sv
core/cva6_mmu/cva6_mmu.sv
core/mult.sv
core/multiplier.sv
core/serdiv.sv
core/perf_counters.sv
core/cva6_mmu/cva6_ptw.sv
core/ariane_regfile_ff.sv
core/scoreboard.sv
core/raw_checker.sv
core/store_buffer.sv
core/cva6_fifo_v3.sv
core/amo_buffer.sv
core/store_unit.sv
core/cva6_mmu/cva6_tlb.sv
core/commit_stage.sv
core/cache_subsystem/wt_dcache_ctrl.sv
core/cache_subsystem/wt_dcache_mem.sv
core/cache_subsystem/wt_dcache_missunit.sv
core/cache_subsystem/wt_dcache_wbuffer.sv
core/cache_subsystem/wt_dcache.sv
core/cache_subsystem/cva6_icache.sv
core/cache_subsystem/cva6_icache_axi_wrapper.sv
core/cache_subsystem/wt_l15_adapter.sv
core/cache_subsystem/wt_cache_subsystem.sv
corev_apu/clint/clint.sv
corev_apu/clint/axi_lite_interface.sv
corev_apu/riscv-dbg/debug_rom/debug_rom.sv
corev_apu/riscv-dbg/src/dm_csrs.sv
corev_apu/riscv-dbg/src/dm_mem.sv
corev_apu/riscv-dbg/src/dm_top.sv
corev_apu/riscv-dbg/src/dmi_cdc.sv
corev_apu/riscv-dbg/src/dmi_jtag.sv
corev_apu/riscv-dbg/src/dm_sba.sv
corev_apu/riscv-dbg/src/dmi_jtag_tap.sv
corev_apu/openpiton/riscv_peripherals.sv
corev_apu/openpiton/ariane_verilog_wrap.sv
corev_apu/rv_plic/rtl/rv_plic_target.sv
corev_apu/rv_plic/rtl/rv_plic_gateway.sv
corev_apu/rv_plic/rtl/plic_regmap.sv
corev_apu/rv_plic/rtl/plic_top.sv
corev_apu/fpga/src/axi2apb/src/axi2apb_wrap.sv
corev_apu/fpga/src/axi2apb/src/axi2apb.sv
corev_apu/fpga/src/axi2apb/src/axi2apb_64_32.sv
corev_apu/fpga/src/axi_slice/src/axi_w_buffer.sv
corev_apu/fpga/src/axi_slice/src/axi_b_buffer.sv
corev_apu/fpga/src/axi_slice/src/axi_slice_wrap.sv
corev_apu/fpga/src/axi_slice/src/axi_slice.sv
corev_apu/fpga/src/axi_slice/src/axi_single_slice.sv
corev_apu/fpga/src/axi_slice/src/axi_ar_buffer.sv
corev_apu/fpga/src/axi_slice/src/axi_r_buffer.sv
corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv
corev_apu/register_interface/src/apb_to_reg.sv
corev_apu/register_interface/src/reg_intf.sv
core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv
core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
core/cvfpu/src/fpnew_cast_multi.sv
core/cvfpu/src/fpnew_classifier.sv
core/cvfpu/src/fpnew_divsqrt_multi.sv
core/cvfpu/src/fpnew_divsqrt_th_64_multi.sv
core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v
core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_ctrl.v
core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_double.v
core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_ff1.v
core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_pack.v
core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_prepare.v
core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_round.v
core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_scalar_dp.v
core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt.v
core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt_radix16_bound_table.v
core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt_radix16_with_sqrt.v
core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_top.v
core/cvfpu/src/fpnew_fma_multi.sv
core/cvfpu/src/fpnew_fma.sv
core/cvfpu/src/fpnew_noncomp.sv
core/cvfpu/src/fpnew_opgroup_block.sv
core/cvfpu/src/fpnew_opgroup_fmt_slice.sv
core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv
core/cvfpu/src/fpnew_rounding.sv
core/cvfpu/src/fpnew_top.sv
core/pmp/src/pmp.sv
core/pmp/src/pmp_entry.sv
core/pmp/src/pmp_data_if.sv
common/local/util/instr_tracer.sv
core/cvxif_example/cvxif_example_coprocessor.sv
core/cvxif_example/instr_decoder.sv
vendor/pulp-platform/common_cells/src/counter.sv
vendor/pulp-platform/common_cells/src/delta_counter.sv
core/cvxif_fu.sv
core/cvxif_issue_register_commit_if_driver.sv
core/cvxif_compressed_if_driver.sv
