!Feature
next_elt_id: 30
name: cfg NA4 access S/U (G=0)
id: 11
display_order: 11
subfeatures: !!omap
- 000_fetch_L0_X1_addr_hit: !Subfeature
    name: 000_fetch_L0_X1_addr_hit
    tag: VP_PMP_F011_S011
    next_elt_id: 1
    display_order: 0
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S011_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X
          permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the privilege mode of the access is S or U (whatever L), then the access
          succeeds only if the R, W, or X bit corresponding to the access type is
          set"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access instruction fetch inside defined NA4
          address range with execute permissions and with L=0\n    - choose an executable
          pmp region and address range\n    - choose only one PMP entry (i)\n\nCONFIGURATION\n\
          \    - pmpcfg(i): A=NA4, X=1, L=0, R/W:random, with reserve on R=0 & W=1\n\
          \    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=0\n\nACCESS\n \
          \   - fetch an instruction from that region (with exact address-matching)\n\
          \nCHECK\n    - check no access-fault exception\n\nREUSABILITY\n    - if
          possible, the PMP entry number (i) is a configurable parameter\n    - if
          possible, the PMP entry lock (L) is a configurable parameter\n    - if possible,
          the PMP entry permissions (R,W,X) are configurable parameters\n    - if
          possible, the PMP entry address-matching mode (A) is a configurable parameter\n\
          \    - if possible, the PMP entry address range (pmpaddr) is a configurable
          parameter\n    - if possible, the PMP entry associated access address is
          a configurable parameter\n    - so a single CONFIGURATION function and a
          single ACCESS function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to
          FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only
          to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege
          mode of the access is S or U (whatever L), then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\n\nTST11-1x(group)
          => FTR01-d\n  [PMP check on instruction fetch where effective privilege
          mode is S or U:\n    - choose an executable pmp region and address range\n\
          \    - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the
          1st one)\n    - if possible, the PMP entry number is a configurable parameter\n\
          \    - choose pmpcfg(i).A=NA4\n    - single access instruction fetch in
          S and U mode]\n  [create scenarios where PMP entries with A=2 (NA4) and
          with/without matching permissions\n    - check only NA4 defined addresses
          are matching]\n TST11-11 (HIGH-PRIO)\n [with L=0 => FTR08-e2-2 (refers to
          FTR09-d2-2),\n  - configure the PMP entry with execute permissions for the
          PMP region\n  - fetch an instruction from that region (with exact address-matching)\n\
          \  - check no access-fault exception]"
- 001_fetch_L0_X0_addr_hit: !Subfeature
    name: 001_fetch_L0_X0_addr_hit
    tag: VP_PMP_F011_S012
    next_elt_id: 1
    display_order: 1
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S012_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X
          permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the privilege mode of the access is S or U (whatever L), then the access
          succeeds only if the R, W, or X bit corresponding to the access type is
          set\n\n{Page 58 Volume II: RISC-V Privileged Architectures V20211203}\n
          Attempting to fetch an instruction from a PMP region that does not have
          execute permissions raises an instruction access-fault exception"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access instruction fetch inside defined NA4
          address range without execute permissions and with L=0\n    - choose an
          executable pmp region and address range\n    - choose only one PMP entry
          (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, X=0, L=0, R/W:random, with
          reserve on R=0 & W=1\n    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=0\n\
          \nACCESS\n    - fetch an instruction from that region (with exact address-matching)\n\
          \nCHECK\n    - check instruction fetch access-fault exception raised\n\n\
          REUSABILITY\n    - if possible, the PMP entry number (i) is a configurable
          parameter\n    - if possible, the PMP entry lock (L) is a configurable parameter\n\
          \    - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\
          \    - if possible, the PMP entry address-matching mode (A) is a configurable
          parameter\n    - if possible, the PMP entry address range (pmpaddr) is a
          configurable parameter\n    - if possible, the PMP entry associated access
          address is a configurable parameter\n    - so a single CONFIGURATION function
          and a single ACCESS function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to
          FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only
          to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege
          mode of the access is S or U (whatever L), then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\n\nFTR04-b\n
          [Attempting to fetch an instruction from a PMP region that does not have
          execute permissions raises an instruction access-fault exception]\n \nTST11-1x(group)
          => FTR01-d\n  [PMP check on instruction fetch where effective privilege
          mode is S or U:\n    - choose an executable pmp region and address range\n\
          \    - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the
          1st one)\n    - if possible, the PMP entry number is a configurable parameter\n\
          \    - choose pmpcfg(i).A=NA4\n    - single access instruction fetch in
          S and U mode]\n  [create scenarios where PMP entries with A=2 (NA4) and
          with/without matching permissions\n    - check only NA4 defined addresses
          are matching]\n TST11-12 (MEDIUM-PRIO)\n[with L=0 => FTR08-e2-2 (refers
          to FTR09-d2-2),\n  - configure the PMP entry without execute permissions
          for the PMP region\n  - fetch an instruction from that region (with exact
          address-matching)\n  - check instruction fetch access-fault exception raised
          => FTR04-b]"
- 002_fetch_L0_X1_addr_miss: !Subfeature
    name: 002_fetch_L0_X1_addr_miss
    tag: VP_PMP_F011_S013
    next_elt_id: 1
    display_order: 2
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S013_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X
          permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the privilege mode of the access is S or U (whatever L), then the access
          succeeds only if the R, W, or X bit corresponding to the access type is
          set"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access instruction fetch from outside defined
          NA4 address range with execute permissions and with L=0\n    - choose an
          executable pmp region and address range\n    - choose only one PMP entry
          (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, X=1, L=0, R/W:random, with
          reserve on R=0 & W=1\n    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=0\n\
          \nACCESS\n    - fetch an instruction from outside all PMP defined regions\n\
          \nCHECK\n    - check instruction fetch access-fault exception raised\n\n\
          REUSABILITY\n    - if possible, the PMP entry number (i) is a configurable
          parameter\n    - if possible, the PMP entry lock (L) is a configurable parameter\n\
          \    - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\
          \    - if possible, the PMP entry address-matching mode (A) is a configurable
          parameter\n    - if possible, the PMP entry address range (pmpaddr) is a
          configurable parameter\n    - if possible, the PMP entry associated access
          address is a configurable parameter\n    - so a single CONFIGURATION function
          and a single ACCESS function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to
          FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only
          to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege
          mode of the access is S or U (whatever L), then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\n\nTST11-1x(group)
          => FTR01-d\n  [PMP check on instruction fetch where effective privilege
          mode is S or U:\n    - choose an executable pmp region and address range\n\
          \    - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the
          1st one)\n    - if possible, the PMP entry number is a configurable parameter\n\
          \    - choose pmpcfg(i).A=NA4\n    - single access instruction fetch in
          S and U mode]\n  [create scenarios where PMP entries with A=2 (NA4) and
          with/without matching permissions\n    - check only NA4 defined addresses
          are matching]\n TST11-13 (MEDIUM-PRIO)\n [with L=0 => FTR08-e2-2 (refers
          to FTR09-d2-2),\n  - configure the PMP entry with execute permissions for
          the PMP region\n  - fetch an instruction from outside all PMP defined regions\n\
          \  - check instruction fetch access-fault exception raised]"
- 003_fetch_L1_X1_addr_hit: !Subfeature
    name: 003_fetch_L1_X1_addr_hit
    tag: VP_PMP_F011_S014
    next_elt_id: 1
    display_order: 3
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S014_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is set, these permissions
          are enforced for all privilege modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the L bit is set, then the access succeeds only if the R, W, or X bit
          corresponding to the access type is set\n\n{Page 60 Section \"Locking and
          Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n
          Locked PMP entries remain locked until the hart is reset"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access instruction fetch inside defined NA4
          address range with execute permissions and with L=1\n    - choose an executable
          pmp region and address range\n    - choose only one PMP entry (i)\n\nCONFIGURATION\n\
          \    - pmpcfg(i): A=NA4, X=1, L=1, R/W:random, with reserve on R=0 & W=1\n\
          \    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=0\n\nACCESS\n \
          \   - fetch an instruction from that region (with exact address-matching)\n\
          \nCHECK\n    - check no access-fault exception\n\nREUSABILITY\n    - if
          possible, the PMP entry number (i) is a configurable parameter\n    - if
          possible, the PMP entry lock (L) is a configurable parameter\n    - if possible,
          the PMP entry permissions (R,W,X) are configurable parameters\n    - if
          possible, the PMP entry address-matching mode (A) is a configurable parameter\n\
          \    - if possible, the PMP entry address range (pmpaddr) is a configurable
          parameter\n    - if possible, the PMP entry associated access address is
          a configurable parameter\n    - so a single CONFIGURATION function and a
          single ACCESS function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to
          FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions
          are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1)
          (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n
          [Locked PMP entries remain locked until the hart is reset]\n\n\nTST11-1x(group)
          => FTR01-d\n  [PMP check on instruction fetch where effective privilege
          mode is S or U:\n    - choose an executable pmp region and address range\n\
          \    - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the
          1st one)\n    - if possible, the PMP entry number is a configurable parameter\n\
          \    - choose pmpcfg(i).A=NA4\n    - single access instruction fetch in
          S and U mode]\n  [create scenarios where PMP entries with A=2 (NA4) and
          with/without matching permissions\n    - check only NA4 defined addresses
          are matching]\n TST11-14 (LOW-PRIO)\n[with L=1 => FTR08-e1 (refers to FTR01-f)
          (refers to FTR09-d2-1),\n  - configure the PMP entry with execute permissions
          for the PMP region\n  - fetch an instruction from that region (with exact
          address-matching)\n  - check no access-fault exception]"
- 004_fetch_L1_X0_addr_hit: !Subfeature
    name: 004_fetch_L1_X0_addr_hit
    tag: VP_PMP_F011_S015
    next_elt_id: 1
    display_order: 4
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S015_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is set, these permissions
          are enforced for all privilege modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the L bit is set, then the access succeeds only if the R, W, or X bit
          corresponding to the access type is set\n\n{Page 60 Section \"Locking and
          Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n
          Locked PMP entries remain locked until the hart is reset\n\n{Page 58 Volume
          II: RISC-V Privileged Architectures V20211203}\nAttempting to fetch an instruction
          from a PMP region that does not have execute permissions raises an instruction
          access-fault exception"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access instruction fetch inside defined NA4
          address range without execute permissions and with L=1\n    - choose an
          executable pmp region and address range\n    - choose only one PMP entry
          (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, X=0, L=1, R/W:random, with
          reserve on R=0 & W=1\n    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=0\n\
          \nACCESS\n    - fetch an instruction from that region (with exact address-matching)\n\
          \nCHECK\n    - check instruction fetch access-fault exception raised\n\n\
          REUSABILITY\n    - if possible, the PMP entry number (i) is a configurable
          parameter\n    - if possible, the PMP entry lock (L) is a configurable parameter\n\
          \    - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\
          \    - if possible, the PMP entry address-matching mode (A) is a configurable
          parameter\n    - if possible, the PMP entry address range (pmpaddr) is a
          configurable parameter\n    - if possible, the PMP entry associated access
          address is a configurable parameter\n    - so a single CONFIGURATION function
          and a single ACCESS function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to
          FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions
          are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1)
          (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n
          [Locked PMP entries remain locked until the hart is reset]\n\nFTR04-b\n
          [Attempting to fetch an instruction from a PMP region that does not have
          execute permissions raises an instruction access-fault exception]\n\nTST11-1x(group)
          => FTR01-d\n  [PMP check on instruction fetch where effective privilege
          mode is S or U:\n    - choose an executable pmp region and address range\n\
          \    - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the
          1st one)\n    - if possible, the PMP entry number is a configurable parameter\n\
          \    - choose pmpcfg(i).A=NA4\n    - single access instruction fetch in
          S and U mode]\n  [create scenarios where PMP entries with A=2 (NA4) and
          with/without matching permissions\n    - check only NA4 defined addresses
          are matching]\n TST11-15 (LOW-PRIO)\n[with L=1 => FTR08-e1 (refers to FTR01-f)
          (refers to FTR09-d2-1),\n  - configure the PMP entry without execute permissions
          for the PMP region\n  - fetch an instruction from that region (with exact
          address-matching)\n  - check instruction fetch access-fault exception raised
          => FTR04-b]"
- 005_fetch_L1_X1_addr_miss: !Subfeature
    name: 005_fetch_L1_X1_addr_miss
    tag: VP_PMP_F011_S016
    next_elt_id: 1
    display_order: 5
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S016_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is set, these permissions
          are enforced for all privilege modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the L bit is set, then the access succeeds only if the R, W, or X bit
          corresponding to the access type is set\n\n{Page 60 Section \"Locking and
          Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n
          Locked PMP entries remain locked until the hart is reset"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access instruction fetch from outside defined
          NA4 address range with execute permissions and with L=1\n    - choose an
          executable pmp region and address range\n    - choose only one PMP entry
          (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, X=1, L=1, R/W:random, with
          reserve on R=0 & W=1\n    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=0\n\
          \nACCESS\n    - fetch an instruction from outside all PMP defined regions\n\
          \nCHECK\n    - check instruction fetch access-fault exception raised\n\n\
          REUSABILITY\n    - if possible, the PMP entry number (i) is a configurable
          parameter\n    - if possible, the PMP entry lock (L) is a configurable parameter\n\
          \    - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\
          \    - if possible, the PMP entry address-matching mode (A) is a configurable
          parameter\n    - if possible, the PMP entry address range (pmpaddr) is a
          configurable parameter\n    - if possible, the PMP entry associated access
          address is a configurable parameter\n    - so a single CONFIGURATION function
          and a single ACCESS function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to
          FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions
          are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1)
          (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n
          [Locked PMP entries remain locked until the hart is reset]\n\nTST11-1x(group)
          => FTR01-d\n  [PMP check on instruction fetch where effective privilege
          mode is S or U:\n    - choose an executable pmp region and address range\n\
          \    - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the
          1st one)\n    - if possible, the PMP entry number is a configurable parameter\n\
          \    - choose pmpcfg(i).A=NA4\n    - single access instruction fetch in
          S and U mode]\n  [create scenarios where PMP entries with A=2 (NA4) and
          with/without matching permissions\n    - check only NA4 defined addresses
          are matching]\n TST11-16 (LOW-PRIO)\n[with L=1 => FTR08-e1 (refers to FTR01-f)
          (refers to FTR09-d2-1),\n  - configure the PMP entry with execute permissions
          for the PMP region\n  - fetch an instruction from outside all PMP defined
          regions\n  - check instruction fetch access-fault exception raised]"
- 006_load_L0_R1_addr_hit: !Subfeature
    name: 006_load_L0_R1_addr_hit
    tag: VP_PMP_F011_S021
    next_elt_id: 1
    display_order: 6
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S021_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X
          permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the privilege mode of the access is S or U (whatever L), then the access
          succeeds only if the R, W, or X bit corresponding to the access type is
          set"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access load or load-reserved instruction
          inside defined NA4 address range with read permissions and with L=0\n  \
          \  - choose a readable pmp region and address range\n    - choose only one
          PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, R=1, L=0, X/W:random\n\
          \    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=0\n\nACCESS\n \
          \   - execute a load or load-reserved instruction from that region (with
          exact address-matching)\n\nCHECK\n    - check no access-fault exception\n\
          \nREUSABILITY\n    - if possible, the PMP entry number (i) is a configurable
          parameter\n    - if possible, the PMP entry lock (L) is a configurable parameter\n\
          \    - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\
          \    - if possible, the PMP entry address-matching mode (A) is a configurable
          parameter\n    - if possible, the PMP entry address range (pmpaddr) is a
          configurable parameter\n    - if possible, the PMP entry associated access
          address is a configurable parameter\n    - so a single CONFIGURATION function
          and a single ACCESS function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to
          FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only
          to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege
          mode of the access is S or U (whatever L), then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\n\nTST11-2x(group)
          => FTR01-d\n  [PMP check on load or load-reserved instruction where effective
          privilege mode is S or U:\n    - choose a data readable pmp region and address
          range\n    - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily
          the 1st one)\n    - if possible, the PMP entry number is a configurable
          parameter\n    - choose pmpcfg(i).A=NA4\n    - single access data load in
          S and U mode when the bit mstatus.MPRV=0]\n  [create scenarios where PMP
          entries with A=2 (NA4) and with/without matching permissions\n    - check
          only NA4 defined addresses are matching]\nTST11-21 (HIGH-PRIO)\n[with L=0
          => FTR08-e2-2 (refers to FTR09-d2-2),\n  - configure the PMP entry with
          read permissions for the PMP region\n  - execute a load or load-reserved
          instruction from that region (with exact address-matching)\n  - check no
          access-fault exception]"
- 007_load_L0_R0_addr_hit: !Subfeature
    name: 007_load_L0_R0_addr_hit
    tag: VP_PMP_F011_S022
    next_elt_id: 1
    display_order: 7
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S022_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X
          permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the privilege mode of the access is S or U (whatever L), then the access
          succeeds only if the R, W, or X bit corresponding to the access type is
          set\n\n{Page 58 Volume II: RISC-V Privileged Architectures V20211203}\n
          Attempting to execute a load or load-reserved instruction which accesses
          a physical address within a PMP region without read permissions raises a
          load access-fault exception"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access load or load-reserved instruction
          inside defined NA4 address range without read permissions and with L=0\n\
          \    - choose a readable pmp region and address range\n    - choose only
          one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, R=0, L=0, X/W:random\n\
          \    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=0\n\nACCESS\n \
          \   - execute a load or load-reserved instruction from that region (with
          exact address-matching)\n\nCHECK\n    - check load access-fault exception
          raised\n\nREUSABILITY\n    - if possible, the PMP entry number (i) is a
          configurable parameter\n    - if possible, the PMP entry lock (L) is a configurable
          parameter\n    - if possible, the PMP entry permissions (R,W,X) are configurable
          parameters\n    - if possible, the PMP entry address-matching mode (A) is
          a configurable parameter\n    - if possible, the PMP entry address range
          (pmpaddr) is a configurable parameter\n    - if possible, the PMP entry
          associated access address is a configurable parameter\n    - so a single
          CONFIGURATION function and a single ACCESS function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to
          FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only
          to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege
          mode of the access is S or U (whatever L), then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\n\nFTR04-c\n
          [Attempting to execute a load or load-reserved instruction which accesses
          a physical address within a PMP region without read permissions raises a
          load access-fault exception]\n\nTST11-2x(group) => FTR01-d\n  [PMP check
          on load or load-reserved instruction where effective privilege mode is S
          or U:\n    - choose a data readable pmp region and address range\n    -
          choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n\
          \    - if possible, the PMP entry number is a configurable parameter\n \
          \   - choose pmpcfg(i).A=NA4\n    - single access data load in S and U mode
          when the bit mstatus.MPRV=0]\n  [create scenarios where PMP entries with
          A=2 (NA4) and with/without matching permissions\n    - check only NA4 defined
          addresses are matching]\nTST11-22 (MEDIUM-PRIO)\n[with L=0 => FTR08-e2-2
          (refers to FTR09-d2-2),\n  - configure the PMP entry without read permissions
          for the PMP region\n  - execute a load or load-reserved instruction from
          that region (with exact address-matching)\n  - check load access-fault exception
          raised => FTR04-c]"
- 008_load_L0_R1_addr_miss: !Subfeature
    name: 008_load_L0_R1_addr_miss
    tag: VP_PMP_F011_S023
    next_elt_id: 1
    display_order: 8
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S023_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X
          permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the privilege mode of the access is S or U (whatever L), then the access
          succeeds only if the R, W, or X bit corresponding to the access type is
          set"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access load or load-reserved instruction
          from outside defined NA4 address range with read permissions and with L=0\n\
          \    - choose a readable pmp region and address range\n    - choose only
          one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, R=1, L=0, X/W:random\n\
          \    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=0\n\nACCESS\n \
          \   - execute a load or load-reserved instruction from outside all PMP defined
          regions\n\nCHECK\n    - check load access-fault exception raised\n\nREUSABILITY\n\
          \    - if possible, the PMP entry number (i) is a configurable parameter\n\
          \    - if possible, the PMP entry lock (L) is a configurable parameter\n\
          \    - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\
          \    - if possible, the PMP entry address-matching mode (A) is a configurable
          parameter\n    - if possible, the PMP entry address range (pmpaddr) is a
          configurable parameter\n    - if possible, the PMP entry associated access
          address is a configurable parameter\n    - so a single CONFIGURATION function
          and a single ACCESS function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to
          FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only
          to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege
          mode of the access is S or U (whatever L), then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\n\nTST11-2x(group)
          => FTR01-d\n  [PMP check on load or load-reserved instruction where effective
          privilege mode is S or U:\n    - choose a data readable pmp region and address
          range\n    - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily
          the 1st one)\n    - if possible, the PMP entry number is a configurable
          parameter\n    - choose pmpcfg(i).A=NA4\n    - single access data load in
          S and U mode when the bit mstatus.MPRV=0]\n  [create scenarios where PMP
          entries with A=2 (NA4) and with/without matching permissions\n    - check
          only NA4 defined addresses are matching]\nTST11-23 (MEDIUM-PRIO)\n[with
          L=0 => FTR08-e2-2 (refers to FTR09-d2-2),\n  - configure the PMP entry with
          read permissions for the PMP region\n  - execute a load or load-reserved
          instruction from outside all PMP defined regions\n  - check load access-fault
          exception raised]"
- 009_load_L1_R1_addr_hit: !Subfeature
    name: 009_load_L1_R1_addr_hit
    tag: VP_PMP_F011_S024
    next_elt_id: 1
    display_order: 9
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S024_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is set, these permissions
          are enforced for all privilege modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the L bit is set, then the access succeeds only if the R, W, or X bit
          corresponding to the access type is set\n\n{Page 60 Section \"Locking and
          Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n
          Locked PMP entries remain locked until the hart is reset"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access load or load-reserved instruction
          inside defined NA4 address range with read permissions and with L=1\n  \
          \  - choose a readable pmp region and address range\n    - choose only one
          PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, R=1, L=1, X/W:random\n\
          \    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=0\n\nACCESS\n \
          \   - execute a load or load-reserved instruction from that region (with
          exact address-matching)\n\nCHECK\n    - check no access-fault exception\n\
          \nREUSABILITY\n    - if possible, the PMP entry number (i) is a configurable
          parameter\n    - if possible, the PMP entry lock (L) is a configurable parameter\n\
          \    - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\
          \    - if possible, the PMP entry address-matching mode (A) is a configurable
          parameter\n    - if possible, the PMP entry address range (pmpaddr) is a
          configurable parameter\n    - if possible, the PMP entry associated access
          address is a configurable parameter\n    - so a single CONFIGURATION function
          and a single ACCESS function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to
          FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions
          are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1)
          (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n
          [Locked PMP entries remain locked until the hart is reset]\n\nTST11-2x(group)
          => FTR01-d\n  [PMP check on load or load-reserved instruction where effective
          privilege mode is S or U:\n    - choose a data readable pmp region and address
          range\n    - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily
          the 1st one)\n    - if possible, the PMP entry number is a configurable
          parameter\n    - choose pmpcfg(i).A=NA4\n    - single access data load in
          S and U mode when the bit mstatus.MPRV=0]\n  [create scenarios where PMP
          entries with A=2 (NA4) and with/without matching permissions\n    - check
          only NA4 defined addresses are matching]\nTST11-24 (LOW-PRIO)\n[with L=1
          => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n  - configure the
          PMP entry with read permissions for the PMP region\n  - execute a load or
          load-reserved instruction from that region (with exact address-matching)\n\
          \  - check no access-fault exception]"
- 010_load_L1_R0_addr_hit: !Subfeature
    name: 010_load_L1_R0_addr_hit
    tag: VP_PMP_F011_S025
    next_elt_id: 1
    display_order: 10
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S025_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is set, these permissions
          are enforced for all privilege modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the L bit is set, then the access succeeds only if the R, W, or X bit
          corresponding to the access type is set\n\n{Page 60 Section \"Locking and
          Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n
          Locked PMP entries remain locked until the hart is reset\n\n{Page 58 Volume
          II: RISC-V Privileged Architectures V20211203}\nAttempting to execute a
          load or load-reserved instruction which accesses a physical address within
          a PMP region without read permissions raises a load access-fault exception"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access load or load-reserved instruction
          inside defined NA4 address range without read permissions and with L=1\n\
          \    - choose a readable pmp region and address range\n    - choose only
          one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, R=0, L=1, X/W:random\n\
          \    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=0\n\nACCESS\n \
          \   - execute a load or load-reserved instruction from that region (with
          exact address-matching)\n\nCHECK\n    - check load access-fault exception
          raised\n\nREUSABILITY\n    - if possible, the PMP entry number (i) is a
          configurable parameter\n    - if possible, the PMP entry lock (L) is a configurable
          parameter\n    - if possible, the PMP entry permissions (R,W,X) are configurable
          parameters\n    - if possible, the PMP entry address-matching mode (A) is
          a configurable parameter\n    - if possible, the PMP entry address range
          (pmpaddr) is a configurable parameter\n    - if possible, the PMP entry
          associated access address is a configurable parameter\n    - so a single
          CONFIGURATION function and a single ACCESS function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to
          FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions
          are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1)
          (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n
          [Locked PMP entries remain locked until the hart is reset]\n\nFTR04-c\n
          [Attempting to execute a load or load-reserved instruction which accesses
          a physical address within a PMP region without read permissions raises a
          load access-fault exception]\n \nTST11-2x(group) => FTR01-d\n  [PMP check
          on load or load-reserved instruction where effective privilege mode is S
          or U:\n    - choose a data readable pmp region and address range\n    -
          choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n\
          \    - if possible, the PMP entry number is a configurable parameter\n \
          \   - choose pmpcfg(i).A=NA4\n    - single access data load in S and U mode
          when the bit mstatus.MPRV=0]\n  [create scenarios where PMP entries with
          A=2 (NA4) and with/without matching permissions\n    - check only NA4 defined
          addresses are matching]\nTST11-25 (LOW-PRIO)\n [with L=1 => FTR08-e1 (refers
          to FTR01-f) (refers to FTR09-d2-1),\n  - configure the PMP entry without
          read permissions for the PMP region\n  - execute a load or load-reserved
          instruction from that region (with exact address-matching)\n  - check load
          access-fault exception raised => FTR04-c]"
- 011_load_L1_R1_addr_miss: !Subfeature
    name: 011_load_L1_R1_addr_miss
    tag: VP_PMP_F011_S026
    next_elt_id: 1
    display_order: 11
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S026_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is set, these permissions
          are enforced for all privilege modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the L bit is set, then the access succeeds only if the R, W, or X bit
          corresponding to the access type is set\n\n{Page 60 Section \"Locking and
          Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n
          Locked PMP entries remain locked until the hart is reset"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access load or load-reserved instruction
          from outside defined NA4 address range with read permissions and with L=1\n\
          \    - choose a readable pmp region and address range\n    - choose only
          one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, R=1, L=1, X/W:random\n\
          \    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=0\n\nACCESS\n \
          \   - execute a load or load-reserved instruction from outside all PMP defined
          regions\n\nCHECK\n    - check load access-fault exception raised\n\nREUSABILITY\n\
          \    - if possible, the PMP entry number (i) is a configurable parameter\n\
          \    - if possible, the PMP entry lock (L) is a configurable parameter\n\
          \    - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\
          \    - if possible, the PMP entry address-matching mode (A) is a configurable
          parameter\n    - if possible, the PMP entry address range (pmpaddr) is a
          configurable parameter\n    - if possible, the PMP entry associated access
          address is a configurable parameter\n    - so a single CONFIGURATION function
          and a single ACCESS function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to
          FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions
          are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1)
          (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n
          [Locked PMP entries remain locked until the hart is reset]\n\nTST11-2x(group)
          => FTR01-d\n  [PMP check on load or load-reserved instruction where effective
          privilege mode is S or U:\n    - choose a data readable pmp region and address
          range\n    - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily
          the 1st one)\n    - if possible, the PMP entry number is a configurable
          parameter\n    - choose pmpcfg(i).A=NA4\n    - single access data load in
          S and U mode when the bit mstatus.MPRV=0]\n  [create scenarios where PMP
          entries with A=2 (NA4) and with/without matching permissions\n    - check
          only NA4 defined addresses are matching]\nTST11-26 (LOW-PRIO)\n[with L=1
          => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n  - configure the
          PMP entry with read permissions for the PMP region\n  - execute a load or
          load-reserved instruction from outside all PMP defined regions\n  - check
          load access-fault exception raised]"
- 012_store_L0_W1_addr_hit: !Subfeature
    name: 012_store_L0_W1_addr_hit
    tag: VP_PMP_F011_S031
    next_elt_id: 1
    display_order: 12
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S031_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X
          permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the privilege mode of the access is S or U (whatever L), then the access
          succeeds only if the R, W, or X bit corresponding to the access type is
          set"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access store, store-conditional, or AMO instruction
          inside defined NA4 address range with write permissions and with L=0\n \
          \   - choose a data writable pmp region and address range\n    - choose
          only one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, W=1, L=0,
          X/R:random\n    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=0\n\n\
          ACCESS\n    - execute a store, store-conditional, or AMO instruction to
          that region (with exact address-matching)\n\nCHECK\n    - check no access-fault
          exception\n\nREUSABILITY\n    - if possible, the PMP entry number (i) is
          a configurable parameter\n    - if possible, the PMP entry lock (L) is a
          configurable parameter\n    - if possible, the PMP entry permissions (R,W,X)
          are configurable parameters\n    - if possible, the PMP entry address-matching
          mode (A) is a configurable parameter\n    - if possible, the PMP entry address
          range (pmpaddr) is a configurable parameter\n    - if possible, the PMP
          entry associated access address is a configurable parameter\n    - so a
          single CONFIGURATION function and a single ACCESS function can be reused
          and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to
          FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only
          to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege
          mode of the access is S or U (whatever L), then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\n\nTST11-3x(group)
          => FTR01-d\n  [PMP check on store, store-conditional, or AMO instruction
          where effective privilege mode is S or U:\n    - choose a data writable
          pmp region and address range\n    - choose only one PMP entry (i) ([FTR02-b1]:
          maybe mandatorily the 1st one)\n    - if possible, the PMP entry number
          is a configurable parameter\n    - choose pmpcfg(i).A=NA4\n    - single
          access data store in S and U mode when the bit mstatus.MPRV=0]\n  [create
          scenarios where PMP entries with A=2 (NA4) and with/without matching permissions\n\
          \    - check only NA4 defined addresses are matching]\nTST11-31 (HIGH-PRIO)\n
          [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2),\n  - configure the PMP entry
          with write permissions for the PMP region\n  - execute a store, store-conditional,
          or AMO instruction to that region (with exact address-matching)\n  - check
          no access-fault exception]"
- 013_store_L0_W0_addr_hit: !Subfeature
    name: 013_store_L0_W0_addr_hit
    tag: VP_PMP_F011_S032
    next_elt_id: 1
    display_order: 13
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S032_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X
          permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the privilege mode of the access is S or U (whatever L), then the access
          succeeds only if the R, W, or X bit corresponding to the access type is
          set\n\n{Page 58 Volume II: RISC-V Privileged Architectures V20211203}\n
          Attempting to execute a store, store-conditional, or AMO instruction which
          accesses a physical address within a PMP region without write permissions
          raises a store access-fault exception"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access store, store-conditional, or AMO instruction
          inside defined NA4 address range without write permissions and with L=0\n\
          \    - choose a data writable pmp region and address range\n    - choose
          only one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, W=0, L=0,
          X/R:random\n    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=0\n\n\
          ACCESS\n    - execute a store, store-conditional, or AMO instruction to
          that region (with exact address-matching)\n\nCHECK\n    - check store access-fault
          exception raised\n\nREUSABILITY\n    - if possible, the PMP entry number
          (i) is a configurable parameter\n    - if possible, the PMP entry lock (L)
          is a configurable parameter\n    - if possible, the PMP entry permissions
          (R,W,X) are configurable parameters\n    - if possible, the PMP entry address-matching
          mode (A) is a configurable parameter\n    - if possible, the PMP entry address
          range (pmpaddr) is a configurable parameter\n    - if possible, the PMP
          entry associated access address is a configurable parameter\n    - so a
          single CONFIGURATION function and a single ACCESS function can be reused
          and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to
          FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only
          to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege
          mode of the access is S or U (whatever L), then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\n\nFTR04-d\n
          [Attempting to execute a store, store-conditional, or AMO instruction which
          accesses a physical address within a PMP region without write permissions
          raises a store access-fault exception]\n\nTST11-3x(group) => FTR01-d\n \
          \ [PMP check on store, store-conditional, or AMO instruction where effective
          privilege mode is S or U:\n    - choose a data writable pmp region and address
          range\n    - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily
          the 1st one)\n    - if possible, the PMP entry number is a configurable
          parameter\n    - choose pmpcfg(i).A=NA4\n    - single access data store
          in S and U mode when the bit mstatus.MPRV=0]\n  [create scenarios where
          PMP entries with A=2 (NA4) and with/without matching permissions\n    -
          check only NA4 defined addresses are matching]\nTST11-32 (MEDIUM-PRIO)\n
          [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2),\n  - configure the PMP entry
          without write permissions for the PMP region\n  - execute a store, store-conditional,
          or AMO instruction to that region (with exact address-matching)\n  - check
          store access-fault exception raised => FTR04-d]"
- 014_store_L0_W1_addr_miss: !Subfeature
    name: 014_store_L0_W1_addr_miss
    tag: VP_PMP_F011_S033
    next_elt_id: 1
    display_order: 14
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S033_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X
          permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the privilege mode of the access is S or U (whatever L), then the access
          succeeds only if the R, W, or X bit corresponding to the access type is
          set"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access store, store-conditional, or AMO instruction
          from outside defined NA4 address range with write permissions and with L=0\n\
          \    - choose a data writable pmp region and address range\n    - choose
          only one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, W=1, L=0,
          X/R:random\n    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=0\n\n\
          ACCESS\n    - execute a store, store-conditional, or AMO instruction to
          outside all PMP defined regions\n\nCHECK\n    - check store access-fault
          exception raised\n\nREUSABILITY\n    - if possible, the PMP entry number
          (i) is a configurable parameter\n    - if possible, the PMP entry lock (L)
          is a configurable parameter\n    - if possible, the PMP entry permissions
          (R,W,X) are configurable parameters\n    - if possible, the PMP entry address-matching
          mode (A) is a configurable parameter\n    - if possible, the PMP entry address
          range (pmpaddr) is a configurable parameter\n    - if possible, the PMP
          entry associated access address is a configurable parameter\n    - so a
          single CONFIGURATION function and a single ACCESS function can be reused
          and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to
          FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only
          to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege
          mode of the access is S or U (whatever L), then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\n\nTST11-3x(group)
          => FTR01-d\n  [PMP check on store, store-conditional, or AMO instruction
          where effective privilege mode is S or U:\n    - choose a data writable
          pmp region and address range\n    - choose only one PMP entry (i) ([FTR02-b1]:
          maybe mandatorily the 1st one)\n    - if possible, the PMP entry number
          is a configurable parameter\n    - choose pmpcfg(i).A=NA4\n    - single
          access data store in S and U mode when the bit mstatus.MPRV=0]\n  [create
          scenarios where PMP entries with A=2 (NA4) and with/without matching permissions\n\
          \    - check only NA4 defined addresses are matching]\nTST11-33 (MEDIUM-PRIO)\n
          [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2),\n  - configure the PMP entry
          with write permissions for the PMP region\n  - execute a store, store-conditional,
          or AMO instruction to outside all PMP defined regions\n  - check store access-fault
          exception raised]"
- 015_store_L1_W1_addr_hit: !Subfeature
    name: 015_store_L1_W1_addr_hit
    tag: VP_PMP_F011_S034
    next_elt_id: 1
    display_order: 15
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S034_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is set, these permissions
          are enforced for all privilege modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the L bit is set, then the access succeeds only if the R, W, or X bit
          corresponding to the access type is set\n\n{Page 60 Section \"Locking and
          Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n
          Locked PMP entries remain locked until the hart is reset"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access store, store-conditional, or AMO instruction
          inside defined NA4 address range with write permissions and with L=1\n \
          \   - choose a data writable pmp region and address range\n    - choose
          only one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, W=1, L=1,
          X/R:random\n    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=0\n\n\
          ACCESS\n    - execute a store, store-conditional, or AMO instruction to
          that region (with exact address-matching)\n\nCHECK\n    - check no access-fault
          exception\n\nREUSABILITY\n    - if possible, the PMP entry number (i) is
          a configurable parameter\n    - if possible, the PMP entry lock (L) is a
          configurable parameter\n    - if possible, the PMP entry permissions (R,W,X)
          are configurable parameters\n    - if possible, the PMP entry address-matching
          mode (A) is a configurable parameter\n    - if possible, the PMP entry address
          range (pmpaddr) is a configurable parameter\n    - if possible, the PMP
          entry associated access address is a configurable parameter\n    - so a
          single CONFIGURATION function and a single ACCESS function can be reused
          and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to
          FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions
          are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1)
          (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n
          [Locked PMP entries remain locked until the hart is reset]\n\nTST11-3x(group)
          => FTR01-d\n  [PMP check on store, store-conditional, or AMO instruction
          where effective privilege mode is S or U:\n    - choose a data writable
          pmp region and address range\n    - choose only one PMP entry (i) ([FTR02-b1]:
          maybe mandatorily the 1st one)\n    - if possible, the PMP entry number
          is a configurable parameter\n    - choose pmpcfg(i).A=NA4\n    - single
          access data store in S and U mode when the bit mstatus.MPRV=0]\n  [create
          scenarios where PMP entries with A=2 (NA4) and with/without matching permissions\n\
          \    - check only NA4 defined addresses are matching]\nTST11-34 (LOW-PRIO)\n
          [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n  - configure
          the PMP entry with write permissions for the PMP region\n  - execute a store,
          store-conditional, or AMO instruction to that region (with exact address-matching)\n\
          \  - check no access-fault exception]"
- 016_store_L1_W0_addr_hit: !Subfeature
    name: 016_store_L1_W0_addr_hit
    tag: VP_PMP_F011_S035
    next_elt_id: 1
    display_order: 16
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S035_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is set, these permissions
          are enforced for all privilege modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the L bit is set, then the access succeeds only if the R, W, or X bit
          corresponding to the access type is set\n\n{Page 60 Section \"Locking and
          Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n
          Locked PMP entries remain locked until the hart is reset\n\n{Page 58 Volume
          II: RISC-V Privileged Architectures V20211203}\nAttempting to execute a
          store, store-conditional, or AMO instruction which accesses a physical address
          within a PMP region without write permissions raises a store access-fault
          exception"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access store, store-conditional, or AMO instruction
          inside defined NA4 address range without write permissions and with L=1\n\
          \    - choose a data writable pmp region and address range\n    - choose
          only one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, W=0, L=1,
          X/R:random\n    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=0\n\n\
          ACCESS\n    - execute a store, store-conditional, or AMO instruction to
          that region (with exact address-matching)\n\nCHECK\n    - check store access-fault
          exception raised\n\nREUSABILITY\n    - if possible, the PMP entry number
          (i) is a configurable parameter\n    - if possible, the PMP entry lock (L)
          is a configurable parameter\n    - if possible, the PMP entry permissions
          (R,W,X) are configurable parameters\n    - if possible, the PMP entry address-matching
          mode (A) is a configurable parameter\n    - if possible, the PMP entry address
          range (pmpaddr) is a configurable parameter\n    - if possible, the PMP
          entry associated access address is a configurable parameter\n    - so a
          single CONFIGURATION function and a single ACCESS function can be reused
          and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to
          FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions
          are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1)
          (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n
          [Locked PMP entries remain locked until the hart is reset]\n\nFTR04-d\n
          [Attempting to execute a store, store-conditional, or AMO instruction which
          accesses a physical address within a PMP region without write permissions
          raises a store access-fault exception]\n\nTST11-3x(group) => FTR01-d\n \
          \ [PMP check on store, store-conditional, or AMO instruction where effective
          privilege mode is S or U:\n    - choose a data writable pmp region and address
          range\n    - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily
          the 1st one)\n    - if possible, the PMP entry number is a configurable
          parameter\n    - choose pmpcfg(i).A=NA4\n    - single access data store
          in S and U mode when the bit mstatus.MPRV=0]\n  [create scenarios where
          PMP entries with A=2 (NA4) and with/without matching permissions\n    -
          check only NA4 defined addresses are matching]\nTST11-35 (LOW-PRIO)\n[with
          L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n  - configure
          the PMP entry without write permissions for the PMP region\n  - execute
          a store, store-conditional, or AMO instruction to that region (with exact
          address-matching)\n  - check store access-fault exception raised => FTR04-d]"
- 017_store_L1_W1_addr_miss: !Subfeature
    name: 017_store_L1_W1_addr_miss
    tag: VP_PMP_F011_S036
    next_elt_id: 1
    display_order: 17
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S036_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is set, these permissions
          are enforced for all privilege modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the L bit is set, then the access succeeds only if the R, W, or X bit
          corresponding to the access type is set\n\n{Page 60 Section \"Locking and
          Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n
          Locked PMP entries remain locked until the hart is reset"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access store, store-conditional, or AMO instruction
          from outside defined NA4 address range with write permissions and with L=1\n\
          \    - choose a data writable pmp region and address range\n    - choose
          only one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, W=1, L=1,
          X/R:random\n    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=0\n\n\
          ACCESS\n    - execute a store, store-conditional, or AMO instruction to
          outside all PMP defined regions\n\nCHECK\n    - check store access-fault
          exception raised\n\nREUSABILITY\n    - if possible, the PMP entry number
          (i) is a configurable parameter\n    - if possible, the PMP entry lock (L)
          is a configurable parameter\n    - if possible, the PMP entry permissions
          (R,W,X) are configurable parameters\n    - if possible, the PMP entry address-matching
          mode (A) is a configurable parameter\n    - if possible, the PMP entry address
          range (pmpaddr) is a configurable parameter\n    - if possible, the PMP
          entry associated access address is a configurable parameter\n    - so a
          single CONFIGURATION function and a single ACCESS function can be reused
          and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to
          FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions
          are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1)
          (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n
          [Locked PMP entries remain locked until the hart is reset]\n\nTST11-3x(group)
          => FTR01-d\n  [PMP check on store, store-conditional, or AMO instruction
          where effective privilege mode is S or U:\n    - choose a data writable
          pmp region and address range\n    - choose only one PMP entry (i) ([FTR02-b1]:
          maybe mandatorily the 1st one)\n    - if possible, the PMP entry number
          is a configurable parameter\n    - choose pmpcfg(i).A=NA4\n    - single
          access data store in S and U mode when the bit mstatus.MPRV=0]\n  [create
          scenarios where PMP entries with A=2 (NA4) and with/without matching permissions\n\
          \    - check only NA4 defined addresses are matching]\nTST11-36 (LOW-PRIO)\n
          [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n  - configure
          the PMP entry with write permissions for the PMP region\n  - execute a store,
          store-conditional, or AMO instruction to outside all PMP defined regions\n\
          \  - check store access-fault exception raised]"
- 018_load_MPP_L0_R1_addr_hit: !Subfeature
    name: 018_load_MPP_L0_R1_addr_hit
    tag: VP_PMP_F011_S041
    next_elt_id: 1
    display_order: 18
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S041_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X
          permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the privilege mode of the access is S or U (whatever L), then the access
          succeeds only if the R, W, or X bit corresponding to the access type is
          set"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access load or load-reserved instruction
          inside defined NA4 address range with read permissions and with L=0\n  \
          \  - choose a readable pmp region and address range\n    - choose only one
          PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, R=1, L=0, X/W:random\n\
          \    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=1 and mstatus.MPP
          contains S or U\n\nACCESS\n    - execute a load or load-reserved instruction
          from that region (with exact address-matching)\n\nCHECK\n    - check no
          access-fault exception\n\nREUSABILITY\n    - if possible, the PMP entry
          number (i) is a configurable parameter\n    - if possible, the PMP entry
          lock (L) is a configurable parameter\n    - if possible, the PMP entry permissions
          (R,W,X) are configurable parameters\n    - if possible, the PMP entry address-matching
          mode (A) is a configurable parameter\n    - if possible, the PMP entry address
          range (pmpaddr) is a configurable parameter\n    - if possible, the PMP
          entry associated access address is a configurable parameter\n    - so a
          single CONFIGURATION function and a single ACCESS function can be reused
          and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to
          FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only
          to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege
          mode of the access is S or U (whatever L), then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\n\nTST11-4x(group)
          => FTR01-d\n  [PMP check on load or load-reserved instruction where effective
          privilege mode is S or U:\n    - choose a data readable pmp region and address
          range\n    - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily
          the 1st one)\n    - if possible, the PMP entry number is a configurable
          parameter\n    - choose pmpcfg(i).A=NA4\n    - single access data load in
          any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U]\n\
          \  [create scenarios where PMP entries with A=2 (NA4) and with/without matching
          permissions\n    - check only NA4 defined addresses are matching]\nTST11-41
          (LOWEST-PRIO)\n [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2),\n  - configure
          the PMP entry with read permissions for the PMP region\n  - execute a load
          or load-reserved instruction from that region (with exact address-matching)\n\
          \  - check no access-fault exception]"
- 019_load_MPP_L0_R0_addr_hit: !Subfeature
    name: 019_load_MPP_L0_R0_addr_hit
    tag: VP_PMP_F011_S042
    next_elt_id: 1
    display_order: 19
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S042_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X
          permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the privilege mode of the access is S or U (whatever L), then the access
          succeeds only if the R, W, or X bit corresponding to the access type is
          set\n\n{Page 58 Volume II: RISC-V Privileged Architectures V20211203}\n
          Attempting to execute a load or load-reserved instruction which accesses
          a physical address within a PMP region without read permissions raises a
          load access-fault exception"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access load or load-reserved instruction
          inside defined NA4 address range without read permissions and with L=0\n\
          \    - choose a readable pmp region and address range\n    - choose only
          one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, R=0, L=0, X/W:random\n\
          \    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=1 and mstatus.MPP
          contains S or U\n\nACCESS\n    - execute a load or load-reserved instruction
          from that region (with exact address-matching)\n\nCHECK\n    - check load
          access-fault exception raised\n\nREUSABILITY\n    - if possible, the PMP
          entry number (i) is a configurable parameter\n    - if possible, the PMP
          entry lock (L) is a configurable parameter\n    - if possible, the PMP entry
          permissions (R,W,X) are configurable parameters\n    - if possible, the
          PMP entry address-matching mode (A) is a configurable parameter\n    - if
          possible, the PMP entry address range (pmpaddr) is a configurable parameter\n\
          \    - if possible, the PMP entry associated access address is a configurable
          parameter\n    - so a single CONFIGURATION function and a single ACCESS
          function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to
          FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only
          to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege
          mode of the access is S or U (whatever L), then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\n\nFTR04-c\n
          [Attempting to execute a load or load-reserved instruction which accesses
          a physical address within a PMP region without read permissions raises a
          load access-fault exception]\n\nTST11-4x(group) => FTR01-d\n  [PMP check
          on load or load-reserved instruction where effective privilege mode is S
          or U:\n    - choose a data readable pmp region and address range\n    -
          choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n\
          \    - if possible, the PMP entry number is a configurable parameter\n \
          \   - choose pmpcfg(i).A=NA4\n    - single access data load in any mode
          when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U]\n  [create
          scenarios where PMP entries with A=2 (NA4) and with/without matching permissions\n\
          \    - check only NA4 defined addresses are matching]\nTST11-42 (LOWEST-PRIO)\n
          [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2),\n  - configure the PMP entry
          without read permissions for the PMP region\n  - execute a load or load-reserved
          instruction from that region (with exact address-matching)\n  - check load
          access-fault exception raised => FTR04-c]"
- 020_load_MPP_L0_R1_addr_miss: !Subfeature
    name: 020_load_MPP_L0_R1_addr_miss
    tag: VP_PMP_F011_S043
    next_elt_id: 1
    display_order: 20
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S043_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X
          permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the privilege mode of the access is S or U (whatever L), then the access
          succeeds only if the R, W, or X bit corresponding to the access type is
          set"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access load or load-reserved instruction
          from outside defined NA4 address range with read permissions and with L=0\n\
          \    - choose a readable pmp region and address range\n    - choose only
          one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, R=1, L=0, X/W:random\n\
          \    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=1 and mstatus.MPP
          contains S or U\n\nACCESS\n    - execute a load or load-reserved instruction
          from outside all PMP defined regions\n\nCHECK\n    - check load access-fault
          exception raised\n\nREUSABILITY\n    - if possible, the PMP entry number
          (i) is a configurable parameter\n    - if possible, the PMP entry lock (L)
          is a configurable parameter\n    - if possible, the PMP entry permissions
          (R,W,X) are configurable parameters\n    - if possible, the PMP entry address-matching
          mode (A) is a configurable parameter\n    - if possible, the PMP entry address
          range (pmpaddr) is a configurable parameter\n    - if possible, the PMP
          entry associated access address is a configurable parameter\n    - so a
          single CONFIGURATION function and a single ACCESS function can be reused
          and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to
          FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only
          to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege
          mode of the access is S or U (whatever L), then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\n\nTST11-4x(group)
          => FTR01-d\n  [PMP check on load or load-reserved instruction where effective
          privilege mode is S or U:\n    - choose a data readable pmp region and address
          range\n    - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily
          the 1st one)\n    - if possible, the PMP entry number is a configurable
          parameter\n    - choose pmpcfg(i).A=NA4\n    - single access data load in
          any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U]\n\
          \  [create scenarios where PMP entries with A=2 (NA4) and with/without matching
          permissions\n    - check only NA4 defined addresses are matching]\nTST11-43
          (LOWEST-PRIO)\n [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2),\n  - configure
          the PMP entry with read permissions for the PMP region\n  - execute a load
          or load-reserved instruction from outside all PMP defined regions\n  - check
          load access-fault exception raised]"
- 021_load_MPP_L1_R1_addr_hit: !Subfeature
    name: 021_load_MPP_L1_R1_addr_hit
    tag: VP_PMP_F011_S044
    next_elt_id: 1
    display_order: 21
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S044_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is set, these permissions
          are enforced for all privilege modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the L bit is set, then the access succeeds only if the R, W, or X bit
          corresponding to the access type is set\n\n{Page 60 Section \"Locking and
          Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n
          Locked PMP entries remain locked until the hart is reset"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access load or load-reserved instruction
          inside defined NA4 address range with read permissions and with L=1\n  \
          \  - choose a readable pmp region and address range\n    - choose only one
          PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, R=1, L=1, X/W:random\n\
          \    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=1 and mstatus.MPP
          contains S or U\n\nACCESS\n    - execute a load or load-reserved instruction
          from that region (with exact address-matching)\n\nCHECK\n    - check no
          access-fault exception\n\nREUSABILITY\n    - if possible, the PMP entry
          number (i) is a configurable parameter\n    - if possible, the PMP entry
          lock (L) is a configurable parameter\n    - if possible, the PMP entry permissions
          (R,W,X) are configurable parameters\n    - if possible, the PMP entry address-matching
          mode (A) is a configurable parameter\n    - if possible, the PMP entry address
          range (pmpaddr) is a configurable parameter\n    - if possible, the PMP
          entry associated access address is a configurable parameter\n    - so a
          single CONFIGURATION function and a single ACCESS function can be reused
          and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to
          FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions
          are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1)
          (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n
          [Locked PMP entries remain locked until the hart is reset]\n\nTST11-4x(group)
          => FTR01-d\n  [PMP check on load or load-reserved instruction where effective
          privilege mode is S or U:\n    - choose a data readable pmp region and address
          range\n    - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily
          the 1st one)\n    - if possible, the PMP entry number is a configurable
          parameter\n    - choose pmpcfg(i).A=NA4\n    - single access data load in
          any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U]\n\
          \  [create scenarios where PMP entries with A=2 (NA4) and with/without matching
          permissions\n    - check only NA4 defined addresses are matching]\nTST11-44
          (LOWEST-PRIO)\n [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n\
          \  - configure the PMP entry with read permissions for the PMP region\n\
          \  - execute a load or load-reserved instruction from that region (with
          exact address-matching)\n  - check no access-fault exception]"
- 022_load_MPP_L1_R0_addr_hit: !Subfeature
    name: 022_load_MPP_L1_R0_addr_hit
    tag: VP_PMP_F011_S045
    next_elt_id: 1
    display_order: 22
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S045_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is set, these permissions
          are enforced for all privilege modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the L bit is set, then the access succeeds only if the R, W, or X bit
          corresponding to the access type is set\n\n{Page 60 Section \"Locking and
          Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n
          Locked PMP entries remain locked until the hart is reset\n\n{Page 58 Volume
          II: RISC-V Privileged Architectures V20211203}\nAttempting to execute a
          load or load-reserved instruction which accesses a physical address within
          a PMP region without read permissions raises a load access-fault exception"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access load or load-reserved instruction
          inside defined NA4 address range without read permissions and with L=1\n\
          \    - choose a readable pmp region and address range\n    - choose only
          one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, R=0, L=1, X/W:random\n\
          \    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=1 and mstatus.MPP
          contains S or U\n\nACCESS\n    - execute a load or load-reserved instruction
          from that region (with exact address-matching)\n\nCHECK\n    - check load
          access-fault exception raised\n\nREUSABILITY\n    - if possible, the PMP
          entry number (i) is a configurable parameter\n    - if possible, the PMP
          entry lock (L) is a configurable parameter\n    - if possible, the PMP entry
          permissions (R,W,X) are configurable parameters\n    - if possible, the
          PMP entry address-matching mode (A) is a configurable parameter\n    - if
          possible, the PMP entry address range (pmpaddr) is a configurable parameter\n\
          \    - if possible, the PMP entry associated access address is a configurable
          parameter\n    - so a single CONFIGURATION function and a single ACCESS
          function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to
          FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions
          are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1)
          (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n
          [Locked PMP entries remain locked until the hart is reset]\n\nFTR04-c\n
          [Attempting to execute a load or load-reserved instruction which accesses
          a physical address within a PMP region without read permissions raises a
          load access-fault exception]\n \nTST11-4x(group) => FTR01-d\n  [PMP check
          on load or load-reserved instruction where effective privilege mode is S
          or U:\n    - choose a data readable pmp region and address range\n    -
          choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n\
          \    - if possible, the PMP entry number is a configurable parameter\n \
          \   - choose pmpcfg(i).A=NA4\n    - single access data load in any mode
          when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U]\n  [create
          scenarios where PMP entries with A=2 (NA4) and with/without matching permissions\n\
          \    - check only NA4 defined addresses are matching]\nTST11-45 (LOWEST-PRIO)\n
          [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n  - configure
          the PMP entry without read permissions for the PMP region\n  - execute a
          load or load-reserved instruction from that region (with exact address-matching)\n\
          \  - check load access-fault exception raised => FTR04-c]"
- 023_load_MPP_L1_R1_addr_miss: !Subfeature
    name: 023_load_MPP_L1_R1_addr_miss
    tag: VP_PMP_F011_S046
    next_elt_id: 1
    display_order: 23
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S046_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is set, these permissions
          are enforced for all privilege modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the L bit is set, then the access succeeds only if the R, W, or X bit
          corresponding to the access type is set\n\n{Page 60 Section \"Locking and
          Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n
          Locked PMP entries remain locked until the hart is reset"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access load or load-reserved instruction
          from outside defined NA4 address range with read permissions and with L=1\n\
          \    - choose a readable pmp region and address range\n    - choose only
          one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, R=1, L=1, X/W:random\n\
          \    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=1 and mstatus.MPP
          contains S or U\n\nACCESS\n    - execute a load or load-reserved instruction
          from outside all PMP defined regions\n\nCHECK\n    - check load access-fault
          exception raised\n\nREUSABILITY\n    - if possible, the PMP entry number
          (i) is a configurable parameter\n    - if possible, the PMP entry lock (L)
          is a configurable parameter\n    - if possible, the PMP entry permissions
          (R,W,X) are configurable parameters\n    - if possible, the PMP entry address-matching
          mode (A) is a configurable parameter\n    - if possible, the PMP entry address
          range (pmpaddr) is a configurable parameter\n    - if possible, the PMP
          entry associated access address is a configurable parameter\n    - so a
          single CONFIGURATION function and a single ACCESS function can be reused
          and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to
          FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions
          are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1)
          (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n
          [Locked PMP entries remain locked until the hart is reset]\n\nTST11-4x(group)
          => FTR01-d\n  [PMP check on load or load-reserved instruction where effective
          privilege mode is S or U:\n    - choose a data readable pmp region and address
          range\n    - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily
          the 1st one)\n    - if possible, the PMP entry number is a configurable
          parameter\n    - choose pmpcfg(i).A=NA4\n    - single access data load in
          any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U]\n\
          \  [create scenarios where PMP entries with A=2 (NA4) and with/without matching
          permissions\n    - check only NA4 defined addresses are matching]\nTST11-46
          (LOWEST-PRIO)\n [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n\
          \  - configure the PMP entry with read permissions for the PMP region\n\
          \  - execute a load or load-reserved instruction from outside all PMP defined
          regions\n  - check load access-fault exception raised]"
- 024_store_MPP_L0_W1_addr_hit: !Subfeature
    name: 024_store_MPP_L0_W1_addr_hit
    tag: VP_PMP_F011_S051
    next_elt_id: 1
    display_order: 24
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S051_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X
          permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the privilege mode of the access is S or U (whatever L), then the access
          succeeds only if the R, W, or X bit corresponding to the access type is
          set"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access store, store-conditional, or AMO instruction
          inside defined NA4 address range with write permissions and with L=0\n \
          \   - choose a data writable pmp region and address range\n    - choose
          only one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, W=1, L=0,
          X/R:random\n    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=1 and
          mstatus.MPP contains S or U\n\nACCESS\n    - execute a store, store-conditional,
          or AMO instruction to that region (with exact address-matching)\n\nCHECK\n\
          \    - check no access-fault exception\n\nREUSABILITY\n    - if possible,
          the PMP entry number (i) is a configurable parameter\n    - if possible,
          the PMP entry lock (L) is a configurable parameter\n    - if possible, the
          PMP entry permissions (R,W,X) are configurable parameters\n    - if possible,
          the PMP entry address-matching mode (A) is a configurable parameter\n   \
          \ - if possible, the PMP entry address range (pmpaddr) is a configurable
          parameter\n    - if possible, the PMP entry associated access address is
          a configurable parameter\n    - so a single CONFIGURATION function and a
          single ACCESS function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to
          FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only
          to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege
          mode of the access is S or U (whatever L), then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\n\nTST11-5x(group)
          => FTR01-d\n  [PMP check on store, store-conditional, or AMO instruction
          where effective privilege mode is S or U:\n    - choose a data writable
          pmp region and address range\n    - choose only one PMP entry (i) ([FTR02-b1]:
          maybe mandatorily the 1st one)\n    - if possible, the PMP entry number
          is a configurable parameter\n    - choose pmpcfg(i).A=NA4\n    - single
          access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP
          contains S or U]\n  [create scenarios where PMP entries with A=2 (NA4) and
          with/without matching permissions\n    - check only NA4 defined addresses
          are matching]\n TST11-51 (LOWEST-PRIO)\n[with L=0 => FTR08-e2-2 (refers
          to FTR09-d2-2),\n  - configure the PMP entry with write permissions for
          the PMP region\n  - execute a store, store-conditional, or AMO instruction
          to that region (with exact address-matching)\n  - check no access-fault
          exception]"
- 025_store_MPP_L0_W0_addr_hit: !Subfeature
    name: 025_store_MPP_L0_W0_addr_hit
    tag: VP_PMP_F011_S052
    next_elt_id: 1
    display_order: 25
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S052_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X
          permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the privilege mode of the access is S or U (whatever L), then the access
          succeeds only if the R, W, or X bit corresponding to the access type is
          set\n\n{Page 58 Volume II: RISC-V Privileged Architectures V20211203}\n
          Attempting to execute a store, store-conditional, or AMO instruction which
          accesses a physical address within a PMP region without write permissions
          raises a store access-fault exception"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access store, store-conditional, or AMO instruction
          inside defined NA4 address range without write permissions and with L=0\n\
          \    - choose a data writable pmp region and address range\n    - choose
          only one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, W=0, L=0,
          X/R:random\n    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=1 and
          mstatus.MPP contains S or U\n\nACCESS\n    - execute a store, store-conditional,
          or AMO instruction to that region (with exact address-matching)\n\nCHECK\n\
          \    - check store access-fault exception raised\n\nREUSABILITY\n    - if
          possible, the PMP entry number (i) is a configurable parameter\n    - if
          possible, the PMP entry lock (L) is a configurable parameter\n    - if possible,
          the PMP entry permissions (R,W,X) are configurable parameters\n    - if
          possible, the PMP entry address-matching mode (A) is a configurable parameter\n\
          \    - if possible, the PMP entry address range (pmpaddr) is a configurable
          parameter\n    - if possible, the PMP entry associated access address is
          a configurable parameter\n    - so a single CONFIGURATION function and a
          single ACCESS function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to
          FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only
          to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege
          mode of the access is S or U (whatever L), then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\n\nFTR04-d\n
          [Attempting to execute a store, store-conditional, or AMO instruction which
          accesses a physical address within a PMP region without write permissions
          raises a store access-fault exception]\n\nTST11-5x(group) => FTR01-d\n \
          \ [PMP check on store, store-conditional, or AMO instruction where effective
          privilege mode is S or U:\n    - choose a data writable pmp region and address
          range\n    - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily
          the 1st one)\n    - if possible, the PMP entry number is a configurable
          parameter\n    - choose pmpcfg(i).A=NA4\n    - single access data store
          in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or
          U]\n  [create scenarios where PMP entries with A=2 (NA4) and with/without
          matching permissions\n    - check only NA4 defined addresses are matching]\n
          TST11-52 (LOWEST-PRIO)\n [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2),\n\
          \  - configure the PMP entry without write permissions for the PMP region\n\
          \  - execute a store, store-conditional, or AMO instruction to that region
          (with exact address-matching)\n  - check store access-fault exception raised
          => FTR04-d]"
- 026_store_MPP_L0_W1_addr_miss: !Subfeature
    name: 026_store_MPP_L0_W1_addr_miss
    tag: VP_PMP_F011_S053
    next_elt_id: 1
    display_order: 26
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S053_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X
          permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the privilege mode of the access is S or U (whatever L), then the access
          succeeds only if the R, W, or X bit corresponding to the access type is
          set"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access store, store-conditional, or AMO instruction
          from outside defined NA4 address range with write permissions and with L=0\n\
          \    - choose a data writable pmp region and address range\n    - choose
          only one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, W=1, L=0,
          X/R:random\n    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=1 and
          mstatus.MPP contains S or U\n\nACCESS\n    - execute a store, store-conditional,
          or AMO instruction to outside all PMP defined regions\n\nCHECK\n    - check
          store access-fault exception raised\n\nREUSABILITY\n    - if possible, the
          PMP entry number (i) is a configurable parameter\n    - if possible, the
          PMP entry lock (L) is a configurable parameter\n    - if possible, the PMP
          entry permissions (R,W,X) are configurable parameters\n    - if possible,
          the PMP entry address-matching mode (A) is a configurable parameter\n   \
          \ - if possible, the PMP entry address range (pmpaddr) is a configurable
          parameter\n    - if possible, the PMP entry associated access address is
          a configurable parameter\n    - so a single CONFIGURATION function and a
          single ACCESS function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to
          FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only
          to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege
          mode of the access is S or U (whatever L), then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\n\nTST11-5x(group)
          => FTR01-d\n  [PMP check on store, store-conditional, or AMO instruction
          where effective privilege mode is S or U:\n    - choose a data writable
          pmp region and address range\n    - choose only one PMP entry (i) ([FTR02-b1]:
          maybe mandatorily the 1st one)\n    - if possible, the PMP entry number
          is a configurable parameter\n    - choose pmpcfg(i).A=NA4\n    - single
          access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP
          contains S or U]\n  [create scenarios where PMP entries with A=2 (NA4) and
          with/without matching permissions\n    - check only NA4 defined addresses
          are matching]\n TST11-53 (LOWEST-PRIO)\n[with L=0 => FTR08-e2-2 (refers
          to FTR09-d2-2),\n  - configure the PMP entry with write permissions for
          the PMP region\n  - execute a store, store-conditional, or AMO instruction
          to outside all PMP defined regions\n  - check store access-fault exception
          raised]"
- 027_store_MPP_L1_W1_addr_hit: !Subfeature
    name: 027_store_MPP_L1_W1_addr_hit
    tag: VP_PMP_F011_S054
    next_elt_id: 1
    display_order: 27
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S054_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is set, these permissions
          are enforced for all privilege modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the L bit is set, then the access succeeds only if the R, W, or X bit
          corresponding to the access type is set\n\n{Page 60 Section \"Locking and
          Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n
          Locked PMP entries remain locked until the hart is reset"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access store, store-conditional, or AMO instruction
          inside defined NA4 address range with write permissions and with L=1\n \
          \   - choose a data writable pmp region and address range\n    - choose
          only one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, W=1, L=1,
          X/R:random\n    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=1 and
          mstatus.MPP contains S or U\n\nACCESS\n    - execute a store, store-conditional,
          or AMO instruction to that region (with exact address-matching)\n\nCHECK\n\
          \    - check no access-fault exception\n\nREUSABILITY\n    - if possible,
          the PMP entry number (i) is a configurable parameter\n    - if possible,
          the PMP entry lock (L) is a configurable parameter\n    - if possible, the
          PMP entry permissions (R,W,X) are configurable parameters\n    - if possible,
          the PMP entry address-matching mode (A) is a configurable parameter\n   \
          \ - if possible, the PMP entry address range (pmpaddr) is a configurable
          parameter\n    - if possible, the PMP entry associated access address is
          a configurable parameter\n    - so a single CONFIGURATION function and a
          single ACCESS function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to
          FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions
          are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1)
          (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n
          [Locked PMP entries remain locked until the hart is reset]\n\nTST11-5x(group)
          => FTR01-d\n  [PMP check on store, store-conditional, or AMO instruction
          where effective privilege mode is S or U:\n    - choose a data writable
          pmp region and address range\n    - choose only one PMP entry (i) ([FTR02-b1]:
          maybe mandatorily the 1st one)\n    - if possible, the PMP entry number
          is a configurable parameter\n    - choose pmpcfg(i).A=NA4\n    - single
          access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP
          contains S or U]\n  [create scenarios where PMP entries with A=2 (NA4) and
          with/without matching permissions\n    - check only NA4 defined addresses
          are matching]\n TST11-54 (LOWEST-PRIO)\n[with L=1 => FTR08-e1 (refers to
          FTR01-f) (refers to FTR09-d2-1),\n  - configure the PMP entry with write
          permissions for the PMP region\n  - execute a store, store-conditional,
          or AMO instruction to that region (with exact address-matching)\n  - check
          no access-fault exception]"
- 028_store_MPP_L1_W0_addr_hit: !Subfeature
    name: 028_store_MPP_L1_W0_addr_hit
    tag: VP_PMP_F011_S055
    next_elt_id: 1
    display_order: 28
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S055_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is set, these permissions
          are enforced for all privilege modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the L bit is set, then the access succeeds only if the R, W, or X bit
          corresponding to the access type is set\n\n{Page 60 Section \"Locking and
          Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n
          Locked PMP entries remain locked until the hart is reset\n\n{Page 58 Volume
          II: RISC-V Privileged Architectures V20211203}\nAttempting to execute a
          store, store-conditional, or AMO instruction which accesses a physical address
          within a PMP region without write permissions raises a store access-fault
          exception"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access store, store-conditional, or AMO instruction
          inside defined NA4 address range without write permissions and with L=1\n\
          \    - choose a data writable pmp region and address range\n    - choose
          only one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, W=0, L=1,
          X/R:random\n    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=1 and
          mstatus.MPP contains S or U\n\nACCESS\n    - execute a store, store-conditional,
          or AMO instruction to that region (with exact address-matching)\n\nCHECK\n\
          \    - check store access-fault exception raised\n\nREUSABILITY\n    - if
          possible, the PMP entry number (i) is a configurable parameter\n    - if
          possible, the PMP entry lock (L) is a configurable parameter\n    - if possible,
          the PMP entry permissions (R,W,X) are configurable parameters\n    - if
          possible, the PMP entry address-matching mode (A) is a configurable parameter\n\
          \    - if possible, the PMP entry address range (pmpaddr) is a configurable
          parameter\n    - if possible, the PMP entry associated access address is
          a configurable parameter\n    - so a single CONFIGURATION function and a
          single ACCESS function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to
          FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions
          are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1)
          (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n
          [Locked PMP entries remain locked until the hart is reset]\n\nFTR04-d\n
          [Attempting to execute a store, store-conditional, or AMO instruction which
          accesses a physical address within a PMP region without write permissions
          raises a store access-fault exception]\n\nTST11-5x(group) => FTR01-d\n \
          \ [PMP check on store, store-conditional, or AMO instruction where effective
          privilege mode is S or U:\n    - choose a data writable pmp region and address
          range\n    - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily
          the 1st one)\n    - if possible, the PMP entry number is a configurable
          parameter\n    - choose pmpcfg(i).A=NA4\n    - single access data store
          in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or
          U]\n  [create scenarios where PMP entries with A=2 (NA4) and with/without
          matching permissions\n    - check only NA4 defined addresses are matching]\n
          TST11-55 (LOWEST-PRIO)\n [with L=1 => FTR08-e1 (refers to FTR01-f) (refers
          to FTR09-d2-1),\n  - configure the PMP entry without write permissions for
          the PMP region\n  - execute a store, store-conditional, or AMO instruction
          to that region (with exact address-matching)\n  - check store access-fault
          exception raised => FTR04-d]"
- 029_store_MPP_L1_W1_addr_miss: !Subfeature
    name: 029_store_MPP_L1_W1_addr_miss
    tag: VP_PMP_F011_S056
    next_elt_id: 1
    display_order: 29
    items: !!omap
    - '000': !VerifItem
        name: '000'
        tag: VP_PMP_F011_S056_I000
        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
          PMP checks are applied to all accesses whose effective privilege mode is
          S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
          Privileged Architectures V20211203}\nWhen the L bit is set, these permissions
          are enforced for all privilege modes\n\n{Page 60 Section \"Priority and
          Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n
          if the L bit is set, then the access succeeds only if the R, W, or X bit
          corresponding to the access type is set\n\n{Page 60 Section \"Locking and
          Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n
          Locked PMP entries remain locked until the hart is reset"
        reqt_doc: ''
        ref_mode: page
        ref_page: ''
        ref_section: ''
        ref_viewer: firefox
        verif_goals: "S or U mode single access store, store-conditional, or AMO instruction
          from outside defined NA4 address range with write permissions and with L=1\n\
          \    - choose a data writable pmp region and address range\n    - choose
          only one PMP entry (i)\n\nCONFIGURATION\n    - pmpcfg(i): A=NA4, W=1, L=1,
          X/R:random\n    - pmpaddr(i): NA4 address range\n    - mstatus.MPRV=1 and
          mstatus.MPP contains S or U\n\nACCESS\n    - execute a store, store-conditional,
          or AMO instruction to outside all PMP defined regions\n\nCHECK\n    - check
          store access-fault exception raised\n\nREUSABILITY\n    - if possible, the
          PMP entry number (i) is a configurable parameter\n    - if possible, the
          PMP entry lock (L) is a configurable parameter\n    - if possible, the PMP
          entry permissions (R,W,X) are configurable parameters\n    - if possible,
          the PMP entry address-matching mode (A) is a configurable parameter\n   \
          \ - if possible, the PMP entry address range (pmpaddr) is a configurable
          parameter\n    - if possible, the PMP entry associated access address is
          a configurable parameter\n    - so a single CONFIGURATION function and a
          single ACCESS function can be reused and combined"
        pfc: 3
        test_type: 3
        cov_method: 1
        cores: -1
        coverage_loc: ''
        comments: "<<Since G=1 the NA4 mode is not selectable>>\n\n<< link to the
          old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date)
          : reading below not mandatory but may help for better understanding >>\n
          \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege
          mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented
          first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to
          FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions
          are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1)
          (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only
          if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n
          [Locked PMP entries remain locked until the hart is reset]\n\nTST11-5x(group)
          => FTR01-d\n  [PMP check on store, store-conditional, or AMO instruction
          where effective privilege mode is S or U:\n    - choose a data writable
          pmp region and address range\n    - choose only one PMP entry (i) ([FTR02-b1]:
          maybe mandatorily the 1st one)\n    - if possible, the PMP entry number
          is a configurable parameter\n    - choose pmpcfg(i).A=NA4\n    - single
          access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP
          contains S or U]\n  [create scenarios where PMP entries with A=2 (NA4) and
          with/without matching permissions\n    - check only NA4 defined addresses
          are matching]\n TST11-56 (LOWEST-PRIO)\n[with L=1 => FTR08-e1 (refers to
          FTR01-f) (refers to FTR09-d2-1),\n  - configure the PMP entry with write
          permissions for the PMP region\n  - execute a store, store-conditional,
          or AMO instruction to outside all PMP defined regions\n  - check store access-fault
          exception raised]"
vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $'
io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $'
config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $'
ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $'
